There has been a multi-picture-element driving liquid crystal display device which has improved viewing angle dependence of gamma characteristic. In the multi-picture-element driving method, one (1) picture element is made up of two or more of sub-picture elements, which have different luminances, so as to improve viewing angle characteristic, i.e., viewing angle dependence of gamma characteristic.
FIG. 9 illustrates a configuration example of a picture element included in such a multi-picture-element driving liquid crystal display device (e.g., refer to Patent Literature 1).
One (1) picture element P is made up of sub-picture elements sp1 and sp2. The sub-picture element sp1 includes a TFT 16a, a sub-picture element electrode 18a, and a storage capacitor 22a. The sub-picture element sp2 includes a TFT 16b, a sub-picture element electrode 18b, and a storage capacitor 22b. 
The TFT 16a and the TFT 16b have (i) respective gate electrodes which are connected with a common gate bus line GL and (ii) respective source electrodes which are connected with a common source bus line SL. The storage capacitor 22a is formed between the sub-picture element electrode 18a and a storage capacitor line CsL1, and the storage capacitor 22b is formed between the sub-picture element electrode 18b and a storage capacitor line CsL2. The storage capacitor line CsL1 extends in parallel with the gate bus line GL such that the sub-picture element sp1 is provided between the storage capacitor line CsL1 and the gate bus line GL. The storage capacitor line CsL2 extends in parallel with the gate bus line GL such that the sub-picture element sp2 is provided between the storage capacitor line CsL2 and the gate bus line GL.
The storage capacitor line CsL1 of each picture element P also serves as a storage capacitor line CsL2, which forms a storage capacitor 22b with a sub-picture element sp2 of another picture element P, which is disposed adjacent to the picture element P such that the storage capacitor line CsL1 is provided between the another picture element P and the picture element P. The storage capacitor line CsL2 of each picture element P also serves as a storage capacitor line CsL1, which forms a storage capacitor 22a with a sub-picture element sp1 of another picture element P, which is disposed adjacent to the picture element P such that the storage capacitor line CsL2 is provided between the another picture element P and the picture element P.
The following describes, with reference to FIGS. 10 and 11, a method for driving the storage capacitor lines CsL1 and CsL2 in a multi-picture-element driving display panel.
Storage capacitor lines CsL (note that “CsL1” and “CsL2” are collectively called “CsL” when “CsL1” and “CsL2” are not distinguished from each other), which are provided in an active area AA (i.e., display area), are connected with respective CS trunk lines bb which are provided in an area adjacent to the active area AA (see FIG. 10). The CS trunk lines bb constitute a CS trunk line group BB. The CS trunk line group BB may be provided only in an area which is disposed adjacent to one of sides of the active area AA in a direction in which the storage capacitor line CsL extends. That is, only one (1) CS trunk line group BB may be provided only on one side of the active area AA. Alternatively, the CS trunk line groups BB may be provided in areas which are adjacent to both sides of the active area AA in the direction in which the storage capacitor line CsL extends. That is, two CS trunk line groups BB may be provided on both sides of the active area AA.
In the case where the CS trunk line group BB is provided only on one side of the active area AA, one end of each of the storage capacitor lines CsL is connected with one of the CS trunk lines bb. In the case where the two CS trunk line groups BB are provided on both sides of the active area AA, one end of each of the storage capacitor lines CsL is connected with one of the CS trunk lines bb of one of the two CS trunk line groups BB, and the other end of the storage capacitor line CsL is connected with one of the CS trunk lines bb of the other of the two CS trunk line groups BB. The CS trunk lines bb extend in a direction perpendicular to the direction in which the storage capacitor lines CsL1 and CsL2 extend. That is, the CS trunk lines bb extend in a direction in which the source bus line SL extends.
FIG. 10 illustrates an example configuration in which two CS trunk line groups BB, each of which is made up of twelve CS trunk lines bb, are provided on both sides of the active area AA. Each of the storage capacitor lines CsL is connected to one of the twelve CS trunk lines bb of each of the two CS trunk line groups BB. The twelve (equal to the number n (n is an even number) of the CS trunk lines bb constituting the CS trunk line group BB) storage capacitor lines CsL, which are sequentially arranged, are connected with the respective twelve CS trunk lines bb of each of the two CS trunk line groups BB. This connection relation of the twelve (i.e., the number n) storage capacitor lines appears repeatedly.
In a case where the CS trunk line group BB is provided only on one side of the active area AA, the n storage capacitor lines CsL, which are sequentially arranged, are connected with the respective n CS trunk lines bb of the CS trunk line group BB. This connection relation of the n storage capacitor lines appears repeatedly.
In each of the case where the CS trunk line group BB is provided only on one side and the case where the two CS trunk line groups BB are provided on both sides, different driving signals, i.e., different storage capacitor voltages are applied to the sequential n storage capacitor lines CsL (see FIG. 11). In each odd-numbered picture element row, two storage capacitor voltages Vcs (e.g., storage capacitor voltages Vcs1 and Vcs2, . . . shown in FIG. 11), which are to be applied to the respective storage capacitor lines CsL1 and CsL2 corresponding to sub-picture elements sp1 and sp2 of a picture element P, have respective binary waveforms in which respective levels change at the same timing and which oscillate in the same cycle. The storage capacitor voltages Vcs are set so that two phases of each of pairs (i.e., n/2 pairs, where n=the number of phases) of the storage capacitor voltages Vcs are gradually shifted at every odd-numbered picture element row. Each of gate pulses Vg (Vg1, Vg3, . . . shown in FIG. 11), which are to be applied to the odd-numbered picture element rows, has a pulse period which (i) appears in a period at which corresponding two storage capacitor voltages Vcs are constant and (ii) ends in sync with a rising edge timing or a falling edge timing of the corresponding two storage capacitor voltages Vcs.
A polarity of the storage capacitor voltage Vcs and a polarity of a data signal, which is to be written into each picture element P, are reversed for each frame. Further, in each one (1) frame, the polarity of the storage capacitor voltages Vcs and the polarity of the data signal are reversed every sequential plurality of horizontal periods.
According to the configuration, first, a data signal is written in a picture element P in a selected one of the odd-numbered picture element rows, and accordingly storage capacitor voltages Vcs applied to the picture element P change. As a result of this, different electric potential variations ΔV, to which a feed-through phenomenon due to capacitors between the gate bus line GL and the sub-picture elements sp1 and sp2 of the picture element P are added, are added to respective picture element electrode potentials of the sub-picture elements sp1 and sp2 into which the identical data signal has been written. This causes the sub-picture elements sp1 and sp2 to have different luminances. From this, an average luminance, which is caused by an effective voltage applied to liquid crystal based on the storage capacitor voltage Vcs in one (1) frame period, causes the entire picture element P to have appropriate gamma characteristic in a wide viewing angle range.
After the odd-numbered picture element rows are scanned, even-numbered picture element rows are scanned similarly. In this case, storage capacitor voltages Vcs in each of the even-numbered picture element rows, which storage capacitor voltages Vcs are applied to respective sub-picture elements sp1 and sp2 of a picture element P, do not have levels which change at the same timing, unlike the storage capacitor voltages Vcs applied to each of the odd-numbered picture element rows. However, after the gate pulse period is ended, the first electric potential change of the picture element electrode is similar to that in the odd-numbered picture element row. Therefore, the gamma characteristic is improved also in the even-numbered picture element rows.
The waveforms of the respective storage capacitor voltages Vcs and the method for scanning are merely examples. The main technical content is to improve the gamma characteristic in the entire picture element P by causing the sub-picture elements sp1 and sp2 to have different luminances by utilizing changes in different storage capacitor voltages Vcs.
Such storage capacitor voltages Vcs are supplied via the respective CS trunk lines bb. Accordingly, storage capacitor voltages Vcs are to be applied to the respective CS trunk lines bb in each of the two CS trunk line groups BB. Accordingly, the storage capacitor voltages Vcs are supplied, from a CS driver (not illustrated), to the respective CS trunk lines bb in the CS trunk line group BB (i.e., the number of phases of the respective storage capacitor voltages Vcs is identical to that of the CS trunk lines bb in the CS trunk line group BB). FIG. 11 illustrates an example in which 12-phase storage capacitor voltages Vcs are supplied. In the case where the two CS trunk line groups BB are provided on both sides of the active area AA (see FIG. 10), an identical storage capacitor voltage Vcs is applied to two CS trunk lines bb, which are connected with an identical storage capacitor line CsL, of the respective two CS trunk line groups BB. According to the configuration, the storage capacitor voltages Vcs are applied from both sides of the active area AA. This makes it possible to suppress a difference in waveform of the storage capacitor voltage Vcs between different parts in the active area AA, which difference is caused due to wiring delay in a large sized liquid crystal screen.